UFS Host Controller (AXI4)

Interface IP

Overview

A UFS host controller sits between the SoC bus and the UFS storage device, turning the transfer descriptors a driver has written into memory into real link transactions. This IP implements that whole path in pure RTL: an AXI4 master fetches descriptors and moves payload data, an APB3 slave exposes the JEDEC UFSHCI 3.0 register model in a 4 KB window, and the transport, UniPro and data-link layers run down to a PHY adapter interface for an external SerDes.

Four asynchronous clock domains — APB, AXI/core, TX link and RX link — are crossed only through structural CDC: gray-coded asynchronous FIFOs, two-flop synchronizers and toggle handshakes, with matching FPGA (XDC) and ASIC (SDC) timing constraints supplied. Error handling is built in rather than bolted on: CRC corruption triggers NAC, a NAC triggers frame replay from a dedicated buffer, and a missing acknowledgement falls back to timer-driven retransmission, all reported through the standard error registers.

Verification is the differentiator. Fifteen functional regressions — link-up, end-to-end 4 KB and 8 KB read/write, multi-frame UPIU reassembly, error injection and recovery, task management, multi-slot round-robin, abort drain, interrupt aggregation, segmented QUERY and a constrained-random stress suite with seed sweeps — all pass on three independent simulators, with 94.35 % RTL statement coverage measured over 25 files.

Scope is stated explicitly rather than implied. This release targets the HS-Gear1, single-lane subset with TC0 and CPort 0 only, and UFSHCI crypto (CE) is not implemented. The M-PHY itself is outside the IP — the controller presents a PHY adapter interface for your SerDes. Higher gears, additional lanes and crypto are scoped as engagement items.