SATA 6Gbps Link / Transport

Domestic SATA Gen3 interface IP

Interface IP

Overview

A SATA Gen3 (6Gbps) Link/Transport semiconductor IP developed in Korea in 2013. It handles the assembly and interpretation of the frames a drive exchanges with the host (Transport layer) and the primitive, CRC and scrambling processing beneath it (Link layer) — the core layers of the storage physical interface.

Owning the interface layer means a performance or compatibility problem in the finished drive is ours to diagnose and fix, not a ticket filed with an external vendor. It is the technical basis of the compatibility record of PaxDisk drives.

Headline specifications — the full specification table follows an NDA
StandardSATA Gen3 (6Gbps)
LayersLink · Transport
Developed in Korea2013

Architecture

Architecture

SATA 6Gbps Link/Transport IP concept block diagram — device-side logic (command queue, buffer, DMA) to the Transport layer (FIS assembly and parsing), the Link layer (primitives, CRC, scrambling) and the external PHY (6Gbps SerDes). The IP covers the Transport and Link layers.

Deliverables

Included with a licence

  • Synthesisable Verilog RTL and integration wrappers
  • Cycle-accurate reference model and equivalence checker
  • Full-chain testbench (clean / correct / UE / pad vectors)
  • Datasheet, manual and integration guide (released under NDA)

Verification toolchains: Intel/Altera (Quartus) · AMD/Xilinx (Vivado) · ASIC — process-portable RTL

Engagement

How we engage

01

IP licence

Licence the verified IP as it stands. Synthesisable RTL, the verification environment and an integration guide come with it.

02

Custom development

The IP is modified or extended to your requirement. Because we design from the interface layer up, unusual requirements can be accommodated.

03

Co-development & national programmes

Joint silicon and firmware development against platform requirements, including participation in national R&D programmes. Scope and terms are agreed case by case.