RV32IMAC RISC-V Core

Processor IP

Overview

Inside a storage controller a processor is always running the firmware — the FTL, command handling, power-loss recovery. This core fills that seat: a 32-bit soft processor implementing the open RISC-V instruction set (RV32IMAC + Zicsr), which no single vendor licences. On top of integer arithmetic it supports multiply/divide (M), atomic operations (A) and the 16-bit compressed encoding (C) that shrinks code size, and each of the three extensions can be switched off by parameter to save area.

The distinguishing structure is a valid-ready handshake at every boundary of the five-stage pipeline. Data advances on valid, and when a downstream stage lowers ready the back-pressure propagates upstream so the whole pipeline halts without losing an instruction. Memory is a 128 KB true dual-port TCM: instruction fetch and data access use separate ports, so they never contend and fetch latency is fixed at one cycle. External peripherals attach through an AXI4-Lite master, and an access to unmapped space traps as a precise exception.

For verification, the same test source builds three configurations — RV32IMAC, RV32IMC and RV32I — and all pass, and eight deliberately injected RTL mutations were all caught by the regression suite. The core is written in pure Verilog-2001 for portability between synthesis tools, and has been confirmed on Intel Arria II GX and AMD Xilinx Artix UltraScale+ devices.