DSP56001 Compatible DSP Core
A 24-bit fixed-point DSP — in active development
DSP IP
Overview
The DSP56001 is a part that stays embedded in audio and industrial equipment long after production ends. This core aims at that gap, implementing a 24-bit fixed-point architecture with two 56-bit accumulators, separate X and Y data buses and a program bus, and address generators with modulo and bit-reverse addressing.
The verification principle is to compare against genuine tool output, never against our own assumptions. Instruction encodings were checked byte by byte against listings from the official Motorola assembler and a reference assembler across four corpora, reaching 97.6–99.2 % coverage with zero mismatches on two of them. The rebuilt datapath — decoder, ALU, address generators, sequencer — executes real DSP kernels, and an FIR filter produces bit-correct results.
| Instruction set | Motorola DSP56000/56001, 24-bit encoding |
|---|---|
| Datapath | 24-bit fixed point, dual 56-bit accumulators (A/B), MAC |
| Buses | Separate X and Y data buses and a program bus |
| Current stage | In development — encoding cross-check complete, scope agreed case by case |
Deliverables
Included with a licence
- Synthesisable Verilog RTL and integration wrappers
- Cycle-accurate reference model and equivalence checker
- Full-chain testbench (clean / correct / UE / pad vectors)
- Datasheet, manual and integration guide (on request)
Verification toolchains: Intel/Altera (Quartus) · AMD/Xilinx (Vivado) · ASIC — process-portable RTL
Engagement
How we engage
01
IP licence
Licence the verified IP as it stands. Synthesisable RTL, the verification environment and an integration guide come with it.
02
Custom development
The IP is modified or extended to your requirement. Because we design from the interface layer up, unusual requirements can be accommodated.
03
Co-development & national programmes
Joint silicon and firmware development against platform requirements, including participation in national R&D programmes. Scope and terms are agreed case by case.
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