TMS320C54x Compatible DSP Core

DSP IP

Overview

The TMS320C54x defined a generation of fixed-point signal processing, and telecom, voice and control equipment still runs code written for it today. This core is instruction-level compatible with that architecture, so C54x assembly and the code built from it carry over rather than being rewritten.

The datapath is built for signal processing rather than general control. One program memory bus and three separate 16-bit data memory buses mean a multiply-accumulate can read both operands and write its result without bus contention. A 40-bit ALU with a 40-bit barrel shifter and two independent 40-bit accumulators sits beside a 17x17 parallel multiplier coupled to a dedicated 40-bit adder, giving a non-pipelined single-cycle MAC, while a compare-select-store unit handles the Viterbi add-compare-select and an exponent encoder computes the exponent of a 40-bit accumulator, each in one cycle.

Addressing is handled by two address generators with eight auxiliary registers and two auxiliary-register arithmetic units, with circular-buffer and block-repeat support. The address space is 192K x 16 — 64K words each of program, data and I/O — and the on-chip peripheral set covers a PLL clock generator, TDM serial port, buffered serial port, 8-bit host port interface, timer, interrupt controller and a software-programmable wait-state generator. The core comes as VHDL RTL with a behavioural model set, testbench and an FPGA synthesis set, alongside an ASIC-level specification covering pinout, memory map, register map and DC/AC characteristics.

The reference implementation described in the specification is on a 0.35 um 3.3 V static CMOS process at 20 ns per single cycle (50 MIPS) in a 144-pin TQFP. On a modern process or an FPGA the operating frequency differs and is characterised for the target.