SSD Controller
1.44MB to 16TB from a single controller
Controller
Overview
In 2012 PaxDisk announced the world's first 2TB SSD on a controller of its own design, and signed an SSD patent agreement with SK hynix the same year. That controller lineage carries the entire defense SSD line-up we ship today.
A single controller architecture covers capacities from 1.44MB to 16TB and supports media from SLC through 3D NAND and STT-MRAM. We design the interface layer, the firmware (FTL) and the ECC ourselves, so a component going end-of-life does not break long-term supply, and a platform-specific requirement can be built rather than worked around.
Controller, interface and error correction held by one company: that vertical integration is the basis of the supply-chain assurance a defense programme has to demonstrate.
| Capacity range | 1.44MB – 16TB (single controller) |
|---|---|
| NAND | SLC · MLC · TLC · 3D NAND · STT-MRAM |
| History | World's first 2TB SSD (2012) · SSD patent agreement with SK hynix |
Architecture
Architecture
Deliverables
Included with a licence
- Synthesisable Verilog RTL and integration wrappers
- Cycle-accurate reference model and equivalence checker
- Full-chain testbench (clean / correct / UE / pad vectors)
- Datasheet, manual and integration guide (released under NDA)
Verification toolchains: Intel/Altera (Quartus) · AMD/Xilinx (Vivado) · ASIC — process-portable RTL
Engagement
How we engage
01
IP licence
Licence the verified IP as it stands. Synthesisable RTL, the verification environment and an integration guide come with it.
02
Custom development
The IP is modified or extended to your requirement. Because we design from the interface layer up, unusual requirements can be accommodated.
03
Co-development & national programmes
Joint silicon and firmware development against platform requirements, including participation in national R&D programmes. Scope and terms are agreed case by case.
More IP
Other IP in the portfolio
Interface IP
SATA 6Gbps Link / Transport
Domestic SATA Gen3 interface IP
ECC
156-bit BCH ECC
Parametric BCH codec, t = 8 … 156
ECC
QC-LDPC Error Correction
Soft-decision error correction for 3D NAND TLC / QLC
Security IP
PBKDF2-HMAC Key Derivation
Password to key — an RFC 8018 hardware engine
Security IP
AES-128/256 Encryption
Combined encrypt/decrypt engine with DMA streaming