156-bit BCH ECC

Parametric BCH codec, t = 8 … 156

ECC

Overview

NAND flash will develop bit errors with time and use. ECC is what corrects them — the last line of defence in SSD reliability — and the higher the correction strength (t), the more degraded a cell can be and still return its data.

This IP is an encoder/decoder codec in which correction strength t is parametric from 8 to 156 bits and sector size from 512B to 1MB. The whole configuration, including the GF(2^m) field size (m = 13…24), is fixed at synthesis, and the 8-bit parallel streaming datapath drops directly into a controller.

As announced in July 2026, the t=156 configuration is a world-class correction strength aimed at the latest NAND process nodes. It is the same engine lineage that goes into our own SSD controllers.

Quote / licensing enquiry Summary datasheet (KO) ← All IP
Headline specifications — the full specification table follows an NDA
CodeShortened BCH over GF(2^m), m = 13…24
Correction strength t8 … 156-bit
Sector size512 B … 1 MB
Datapath8-bit parallel, 1 byte/cycle streaming

Architecture

Architecture

BCH ECC encoder/decoder block diagram — the encode path (data to BCH encoder to codeword) and the decode path (syndrome, Berlekamp–Massey, Chien search, gated XOR correction).

Deliverables

Included with a licence

  • Synthesisable Verilog RTL and integration wrappers
  • Cycle-accurate reference model and equivalence checker
  • Full-chain testbench (clean / correct / UE / pad vectors)
  • Datasheet, manual and integration guide (released under NDA)

Verification toolchains: Intel/Altera (Quartus) · AMD/Xilinx (Vivado) · ASIC — process-portable RTL

Engagement

How we engage

01

IP licence

Licence the verified IP as it stands. Synthesisable RTL, the verification environment and an integration guide come with it.

02

Custom development

The IP is modified or extended to your requirement. Because we design from the interface layer up, unusual requirements can be accommodated.

03

Co-development & national programmes

Joint silicon and firmware development against platform requirements, including participation in national R&D programmes. Scope and terms are agreed case by case.

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