AES-128/256 Encryption
Combined encrypt/decrypt engine with DMA streaming
Security IP
Overview
AES is the stage that encrypts the actual data with the key PBKDF2 produced. This IP is a combined engine in which one core handles key expansion, encryption and decryption, with the 128-bit or 256-bit key selected through a control register (10 or 14 rounds).
There are two operating modes: a single-block mode driven a block at a time through registers, and a DMA streaming mode in which a length is given and 128-bit blocks run continuously out through an AXI 64-bit master. Separate clock domains for APB control and AXI data keep controller integration straightforward.
The implementation is area-efficient — a 32-bit word-serial datapath sharing four S-Boxes — and is designed to be integrated into an SSD controller datapath. It completes the storage security chain of key derivation (PBKDF2), encryption (AES) and error correction (ECC) with domestic IP throughout.
| Algorithm | AES (FIPS 197) — selectable 128/256-bit key, 10/14 rounds |
|---|---|
| Operation | Single core for encryption and decryption · key expansion on board |
| Interface | APB control + AXI 64-bit DMA streaming (continuous multi-block) |
| Implementation | Area-efficient 32-bit word-serial datapath · simulation testbench available |
Architecture
Architecture
Deliverables
Included with a licence
- Synthesisable Verilog RTL and integration wrappers
- Cycle-accurate reference model and equivalence checker
- Full-chain testbench (clean / correct / UE / pad vectors)
- Datasheet, manual and integration guide (released under NDA)
Verification toolchains: Intel/Altera (Quartus) · AMD/Xilinx (Vivado) · ASIC — process-portable RTL
Engagement
How we engage
01
IP licence
Licence the verified IP as it stands. Synthesisable RTL, the verification environment and an integration guide come with it.
02
Custom development
The IP is modified or extended to your requirement. Because we design from the interface layer up, unusual requirements can be accommodated.
03
Co-development & national programmes
Joint silicon and firmware development against platform requirements, including participation in national R&D programmes. Scope and terms are agreed case by case.
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